1. Field of the Invention
The present invention relates to a plasma display apparatus.
2. Description of Related Art
Plasma display panels are nowadays drawing attention as a type of thin-shape flat display device.
FIG. 1 is a diagram schematically showing the construction of a plasma display apparatus having a plasma display panel mounted therein.
In FIG. 1, a PDP 10 as a typical plasma display panel comprises: m column electrodes Z1 to Zm; and n row electrodes X1 to Xn and n row electrodes Y1 to Yn arranged so as to cross the column electrodes, respectively. The row electrodes X1 to Xn and row electrodes Y1 to Yn constitute a first display line to an nth display line in the PDP 10 by pairs of row electrodes Xi (1≦i≦n) and Yi (1≦i≦n), respectively. A discharge space filled with a discharge gas is formed between the column electrodes Z and the row electrodes X and Y. A discharge cell which performs a discharge light emission in red color, a discharge cell which performs a discharge light emission in green color, or a discharge cell which performs a discharge light emission in blue color is formed at each of intersecting portions of each row electrode pair and the column electrode that include the discharge space. Since each discharge cell emit light by using a discharge phenomenon, only two states, “light emitting state” associated with the discharge and “light-off state” can be taken by the discharge cell. That is, each discharge cell can express only luminance of two gradations of the lowest luminance and the highest luminance.
The driving apparatus 100, therefore, performs the gradation driving using a subfield method so as to realize a luminance display of a halftone corresponding to a video signal in the PDP 10 having the discharge cells. According to the subfield method, a display period of one field is divided into a plurality of subfields, and a discharge light emitting period corresponding to the subfield is allocated to each subfield. Each discharge cell is allowed to selectively perform the discharge light emission only for the allocated period of time for each subfield in accordance with the input video signal.
FIG. 2 is a diagram showing various driving pulses which are applied by the driving apparatus 100 to the row electrode pair and the column electrode of the PDP 10 in one subfield and their timings of applications in order to execute the gradation driving as mentioned above. A row electrode driver and a column electrode driver (not shown) for generating the various driving pulses are provided for the driving apparatus 100.
In an all-resetting step Rc in FIG. 2, the row electrode driver generates reset pulses RPX of a positive polarity and reset pulses RPY of a negative polarity, respectively, and applies them to the row electrodes X1 to Xn and the row electrodes Y1 to Yn as shown in FIG. 2, respectively. In accordance with the application of the reset pulses RPX and RPY, all of the discharge cells of the PDP 10 are subjected to a reset discharge, and a predetermined amount of wall charges are uniformly formed in each discharge cell.
Subsequently, in an address step Wc, the driving apparatus 100 forms pixel data corresponding to each discharge cell based on the input video signal. The column electrode driver generates pixel data pulses having a pulse voltage corresponding to a logic level of each pixel data. For example, when the pixel data has the logic level “1”, the column electrode driver generates the pixel data pulses having a pulse voltage of a high voltage. When the pixel data has the logic level “0”, the column electrode driver generates the pixel data pulses having a pulse voltage of a low voltage (0 volt). The column electrode driver sequentially applies pixel data pulse groups DP1, DP2, . . . , DPn obtained by grouping the pixel data pulses for each display line (m pulses) to the column electrodes Z1 to Zm as shown in FIG. 2. During this period, the row electrode driver generates scanning pulses SP of a negative polarity as shown in FIG. 2 synchronously with the timing of the application of each pixel data pulse group DP and sequentially applies them to the row electrodes Y1 to Yn. Consequently, a discharge (selective erasure discharge) occurs only in the discharge cell existing in a intersecting portion of the display line to which the scanning pulse SP has been applied and the “column” to which the pixel data pulse of a high voltage has been applied. Wall charges formed in the discharge cell are extinguished.
Subsequently, in a light emission sustaining step Ic, as shown in FIG. 2, the row electrode driver alternately and repetitively generates sustaining pulses IPX and IPY of a positive polarity and applies them to the row electrodes X1 to Xn and the row electrodes Y1 to Yn, respectively. In the light emission sustaining step Ic, the number of sustaining pulses IPX and IPY which are repetitively applied is equal to the number of times corresponding to the discharge light emitting period allocated to each subfield as mentioned above. In accordance with the application of those sustaining pulses IP, only the discharge cell in which the wall charges remain in the discharge space discharges (sustaining discharge) each time the sustaining pulses IPX and IPY are applied. That is, only the discharge cell in which the selective erasure discharge is not caused in the address step Wc repeats the light emission associated by the sustaining discharge for a period of time allocated to each subfield and maintains the light emitting state.
The driving apparatus 100 controls the row electrode driver and column electrode driver so as to execute a series of operations comprising all-resetting step Rc, address step Wc, and light emission sustaining step Ic for each subfield. According to the above-described control scheme, the light emission associated with the sustaining discharge is performed during the display period of one field a number of times corresponding to the luminance level of the input video signal. In this process, visually, an intermediate luminance according to the number of times of the executed light emission is expressed during the display period of one field.
Since the various driving pulses as mentioned above have a relatively high voltage, if the driver for generating the driving pulses operates erroneously and is short-circuited therein, a large current flows into the driver for a long period of time, so that an excessive power loss occurs continuously. To prevent it, an excessive current detecting circuit to detect an excessive current is provided on a common power line for supplying a power voltage to each driver, and a power shut-off circuit to forcedly shut off the power source upon detection of the excessive current is provided. In this instance, since the column electrode driver is actually constructed by m independent drivers corresponding to the column electrodes Z1 to Zm, an amount of current flowing on the common power line also depends on the pixel data. A problem, therefore, such that even if one driver in the column electrode driver is short-circuited therein and a large current flows in the driver and its influence is reflected onto the common power line, whether it is caused by the excessive current or not cannot be easily discriminated occurs. That is, it is because even if each driver functions normally, there is a case where the pixel data pulses of the high voltage are generated simultaneously from many drivers in dependence on the pixel data, and in this instance, a large current flows on the common power line.